DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm

Computation in several real-world applications like probabilistic machine learning, sparse linear algebra, and robotic navigation, can be modeled as irregular directed acyclic graphs (DAGs). The data dependencies DAGs pose challenges to parallel execution on general-purpose CPUs GPUs, resulting severe under-utilization of the hardware. This paper proposes DPU, a specialized processor designed for efficient DAGs. DPU is equipped with compute units that execute different subgraphs DAG independently. synchronize within cycle using hardware-supported synchronization primitive, communicate via an interconnect global banked scratchpad. Furthermore, precision-scalable posit arithmetic unit developed enable application-dependent precision. taped-out 28nm CMOS, achieving speedup 5.1$\times$ 20.6$\times$ over state-of-the-art CPU GPU implementations algebra learning workloads. performance achieved while operating at power budget 0.23W, opposed 55W 98W GPU, peak efficiency 538 GOPS/W which 1350$\times$ 9000$\times$ higher than respectively. Thus, architecture, enables low-power